FIG. 1 illustrates a known circuit for performing a zero detection, via a zero detection circuit 12, for an adder 10. The zero detection circuit 12 is required to wait on the completion of the addition in adder 10 before generating the output. If the carry-in input to the adder arrives late relative to the input operands, the delay for the output of the zero detection circuit is a function of the carry-in delay, the completion of the adder once the carry-in signal is stable, and the delay through the zero detection logic. Using conventional static circuitry, this added time can be excessive for circuitry in which the all.sub.-- zero signal of FIG. 1 is in the critical path. The presence of the zero detection circuit in the sum data path adds loading to the outputs of the adder, which can create additional delay for the resolution of the sum.
Another known method for performing zero detection is performed parallel with the addition, however, no capability exists for inclusion of a carry-in from an operation on lower order bits of operands A and B. The exclusion of the carry-in bit results in an inability to perform zero detection on a select group of bits, out of the two operands A and B. Instead, all bits of the two operands A and B must be input to the zero detect logic which increases the surface area of circuitry.